1. Field of the Invention
The present invention relates to an integrated circuit and a testing method for the integrated circuit, and more particularly to an integrated circuit having an input terminal for testing and a test-use logic circuit capable of setting a plurality of test modes and to a method for testing such an circuit.
2. Description of the Related Art
In the case of highly integrated semiconductor circuits, each semiconductor device of the circuit is tested before the circuit is completed in order to see if the device has the prescribed characteristics and performs the intended functions. However, as the functions of each device become more sophisticated it is increasingly inefficient to test every function of the device. It is therefore typical to test an integrated circuit chip by setting a test mode which is suitable for testing but different from the actual state of use. As the integrated circuit chips have more multi-functional in recent years, efforts have been made to improve test efficiency by providing an increasing number of test modes according to test purpose.
Heretofore, setting of such test modes has been accomplished by providing special test input terminals or pins for receiving test mode setting date. Additionally, a further special test input terminal is provided for switching the mode between actual use and test. Also, setting of test modes may be accomplished by allocating a specific terminal for mode setting at the time of test mode only.
In the above described arrangements, the former arrangement requires an increase in the number of pins, while the latter arrangement results in an increase in test time because the terminal allocated for test mode setting is assigned a role in the test mode and the terminal is not able to be tested in the test mode. Therefore, a longer test time is required for testing the integrated circuit in the actual use mode.
Thus, in view of the difficulties with the above describes arrangements, it is an object of the present invention to provide an integrated circuit capable of setting a plurality of test modes with a simple circuit by using only one input terminal as a test terminal for switching between the actual use and the test modes.
Another object of the present invention is to provide a method for testing such integrated circuits.